1. Technical Field
The present disclosure refers to electrical interconnection devices for integrated circuits in chip of semiconductor material, generally known as pads. Particularly, the present disclosure refers to techniques of locating faults of pads and integrated logic circuit which controls the inputs of pads.
2. Description of the Related Art
FIG. 1 schematically shows a pad 1000 of known type and comprising terminals or pins 16PA-25PA and an input-output terminal 70PA adapted to be connected, by a bonding wire, to a pin (not shown) of the integrated circuit package associated with the pad 1000 itself.
As shown in FIG. 1, pad 1000 is provided with buffers 28PA and 30PA, an analog switch 29PA and gates 33PA and 34PA. Moreover, pad 1000 is provided with a pull-up resistor R1PA and pull-down resistor R2PA enabling to adapt electrical currents and voltages which involve the pad 1000 to values predicted for the integrated circuit to which is connected the pad 1000 or to the electronic circuit outside the pad 1000.
Pins 16PA-25PA are connected to an integrated analog, digital, logic circuit 400PA which controls or monitors pins 16PA-25PA.
In the manufacturing of an integrated circuit, it is very important to detect faults (or defects) exhibited by the pad and the integrated logic circuit controlling the inputs of pads.
With reference to the faults of the pad and digital portion of the circuit 400PA, are known the EWS, Electrical Wafer Sort and Final Test tests. The EWS test is performed on a semiconductor wafer before connecting the pads to the pins of the package and, moreover, it is possible to predict that all the pins of the pad have not been tested. The Final Test evaluates the pad after a package has been applied to the corresponding integrated circuit. The tests are performed by providing to the pins corresponding to the digital signals (16PA-19PA, 22PA, 24PA, 25PA) specific patterns of signals which should allow to detect the faults by a signal at the pin 22PA and input-output terminal 70PA.
Moreover, for detecting the faults of the integrated logic circuit 400PA, it is known the use of trees of X-OR gates, connected to some of the digital pins 16PA-25PA. The output value of the tree of X-OR gates should reveal a defect of the logic circuit 400.
To this end, in FIG. 1, it is shown an X-OR gate, LP1 of such tree having an input directly connected to the pin 16PA which is electrically connected to the logic circuit 400PA by interposing decoupling buffers B1-B4. In this case, it is likely to detect also possible faults associated to the decoupling buffers B1-B4 by suitably monitoring the output of the tree of gates X-OR.
In another case, the tree of X-OR gates can comprise a gate LP2 having an input connected to the pin 16PA by decoupling buffers B2-B4. In this second case, it is not possible to detect also the possible faults associated to the decoupling buffers B2-B4 which follow the node N to which is connected the gate X-OR, LP2. The position of node N along the chain of buffers B1-B4 is not easily obtainable with precision during the layout step of the integrated circuit because, from a standpoint logic view, the operations of gates LP1 and LP2 are identical.
In any case, the Applicant observes that such trees of gates X-OR, used according to the prior art do not enable to detect the faults associated with a pad 1000.
According to a prevalent modeling of faults, a defect searched by the tests is of the kind of “stuck at” 0 or 1, due to this defect a given pin or point of the circuit of the pad is forcedly at a voltage value to which is associated the logic value 0 or 1, independently from its real operative condition.
Due to this possibility of detecting faults of circuits, it is known the use of providing a classification of faults well known by the person skilled in the art. For example, the term “detected for stuck at 0 or 1” means that there is always at least one pattern of input signals which enables to activate and propagate the fault so that the latter can be reliably detected at an exit pin. According to another example, the term “Undetectable” means that the fault can not be determined because it is not possible to detect a pattern of input signals enabling to activate and propagate the fault so that the latter can be reliably located at an exit pin.